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CY62256N
256K (32K x 8) Static RAM
256K (32K x 8) Static RAM
Features
Functional Description
The CY62256N[1] is a high performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers. This device has an automatic power down feature, reducing the power consumption by 99.9 percent when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.
Temperature Ranges Commercial: 0 C to +70 C Industrial: -40 C to +85 C Automotive-A: -40 C to +85 C Automotive-E: -40 C to +125 C High Speed: 55 ns Voltage Range: 4.5 V to 5.5 V Operation Low Active Power 275 mW (max) Low Standby Power (LL version) 82.5 W (max) Easy Memory Expansion with CE and OE Features TTL-Compatible Inputs and Outputs Automatic Power Down when Deselected CMOS for Optimum Speed and Power Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP, 28-pin (300-mil) Narrow SOIC, 28-pin TSOP-I, and 28-pin Reverse TSOP-I Packages

Logic Block Diagram
INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER
I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5
32K x 8 Y ARRA
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note 1. For best practice recommendations, do refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document Number: 001-06511 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 4, 2011
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CY62256N
Contents
Product Portfolio .............................................................. 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 6 Typical DC and AC Characteristics ................................ 9 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14
Document Number: 001-06511 Rev. *D
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CY62256N
Product Portfolio
Product CY62256NLL CY62256NLL CY62256NLL CY62256NLL Commercial Industrial Automotive-A Automotive-E Min 4.5 VCC Range (V) Typ[2] 5.0 Max 5.5 Speed (ns) 70 55/70 55/70 55 Power Dissipation Operating, ICC Standby, ISB2 (A) (mA) [2] Typ Max Typ[2] Max 25 50 0.1 5 25 50 0.1 10 25 50 0.1 10 25 50 0.1 15
Pin Configurations
Figure 1. 28-pin DIP and Narrow SOIC Figure 2. 28-pin TSOP I and Reverse TSOP I
Table 1. Pin Definitions Pin Number 1-10, 21, 23-26 11-13, 15-19, 27 20 22 14 28 Type Input Input/Output Input/Control Input/Control Input/Control Ground Power Supply Description A0-A14. Address Inputs I/O0-I/O7. Data lines. Used as input or output lines depending on operation WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted CE. When LOW, selects the chip. When HIGH, deselects the chip OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins GND. Ground for the device VCC. Power supply for the device
Note 2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document Number: 001-06511 Rev. *D
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CY62256N
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ -65 C to +150 C Ambient temperature with power applied ........................................... -55 C to +125 C Supply voltage to ground potential (pin 28 to pin 14)...........................................-0.5 V to +7.0 V DC voltage applied to outputs in high Z State[3] .................................. -0.5 V to VCC + 0.5 V DC input voltage[3] ............................... -0.5 V to VCC + 0.5 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, method 3015) Latch up current..................................................... > 200 mA
Operating Range
Range Commercial Industrial Automotive-A Automotive-E Ambient Temperature (TA)[4] 0 C to +70 C -40 C to +85 C -40 C to +85 C -40 C to +125 C VCC 5 V 10% 5 V 10% 5 V 10% 5 V 10%
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current GND < VI < VCC GND < VO < VCC, output disabled VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC LL-Commercial LL - Industrial LL - Auto-A LL - Auto-E ISB1 Automatic CE power down current-- TTL inputs Max. VCC, CE > VIH, LL-Commercial VIN > VIH or VIN < VIL, LL - Industrial f = fMAX LL - Auto-A LL - Auto-E ISB2 Automatic CE power down current-- CMOS inputs Max. VCC, LL-Commercial CE > VCC 0.3 V LL - Industrial VIN > VCC 0.3 V, or LL - Auto-A VIN < 0.3 V, f = 0 LL - Auto-E Test Conditions VCC = Min, IOH = 1.0 mA VCC = Min, IOL = 2.1 mA -55 Min 2.4 - 2.2 -0.5 -0.5 -0.5 - - - - - - - - - - - - Typ[5] - - - - - - - 25 25 25 - 0.3 0.3 0.3 - 0.1 0.1 0.1 Max - 0.4 VCC + 0.5 V 0.8 +0.5 +0.5 - 50 50 50 - 0.5 0.5 0.5 - 10 10 15 Min 2.4 - 2.2 -0.5 -0.5 -0.5 - - - - - - - - - - - - -70 Typ[5] - - - - - - 25 25 25 - 0.3 0.3 0.3 - 0.1 0.1 0.1 - Max - 0.4 VCC + 0.5 V 0.8 +0.5 +0.5 50 50 50 - 0.5 0.5 0.5 - 5 10 10 - Unit V V V V A A mA mA mA mA mA mA mA mA A A A A
Capacitance
Parameter[6] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max 6 8 Unit pF pF
Notes 3. VIL (min) = 2.0 V for pulse durations of less than 20 ns. 4. TA is the "Instant-On" case temperature. 5. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. 6. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-06511 Rev. *D
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Thermal Resistance
Parameter[7] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Still air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board DIP 75.61 43.12 SOIC 76.56 36.07 TSOP 93.89 24.64 RTSOP 93.89 24.64 Unit C/W C/W
Figure 3. AC Test Loads and Waveforms
5V OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 990 R1 1800 R1 1800 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 990 3.0 V GND 10% ALL INPUT PULSES 90% 90% 10% < 5 ns
< 5 ns
(a)
(b)
Equivalent to: THE VENIN EQUIVALENT 639 OUTPUT 1.77 V
Data Retention Characteristics
Parameter VDR ICCDR Description VCC for data retention Data retention current LL - Commercial LL - Auto-E tCDR[7] tR
[7]
Conditions[8]
Min 2.0 - - - 0 tRC
Typ[9] - 0.1 0.1 0.1 - -
Max - 5 10 10 - -
Unit V A A A ns ns
VCC = 2.0V, CE > VCC 0.3V, LL - Industrial/Auto-A VIN > VCC 0.3V, or VIN < 0.3V
Chip deselect to data retention time Operation recovery time
Figure 4. Data Retention Waveform
DATA RETENTION MODE VCC CE 3.0 V tCDR VDR > 2 V 3.0 V tR
Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. No input may exceed VCC + 0.5 V. 9. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document Number: 001-06511 Rev. *D
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CY62256N
Switching Characteristics
Over the Operating Range[10] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low Z[11] OE HIGH to high Z CE LOW to low CE HIGH to high
[11, 12]
Description
CY62256N-55 Min 55 - 5 - - 5 - 5 - 0 - 55 45 45 0 0 40 25 0 - 5 Max - 55 - 55 25 - 20 - 20 - 55 - - - - - - - - 20 -
CY62256N-70 Min 70 - 5 - - 5 - 5 - 0 - 70 60 60 0 0 50 30 0 - 5 Max - 70 - 70 35 - 25 - 25 - 70 - - - - - - - - 25 -
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Z[11] Z[11, 12]
CE LOW to power up CE HIGH to power down
[13, 14]
Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE LOW to high Z[11, 12] WE HIGH to low Z[11]
Switching Waveforms
Figure 5. Read Cycle No. 1[15, 16]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes 10. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 11. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 12. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 13. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 14. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 15. Device is continuously selected. OE, CE = VIL. 16. WE is HIGH for Read cycle.
Document Number: 001-06511 Rev. *D
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Switching Waveforms
(continued) Figure 6. Read Cycle No. 2[17, 18]
CE tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50%
tRC
tHZOE tHZCE DATA VALID tPD
HIGH IMPEDANCE
ICC 50% ISB
Figure 7. Write Cycle No. 1 (WE Controlled)[19, 20, 21]
tWC ADDRESS
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O NOTE 22 tHZOE DATAIN VALID tHD
Figure 8. Write Cycle No. 2 (CE Controlled)[19, 20, 21]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATA VALID IN tHD tHA tSCE
Notes 17. WE is HIGH for Read cycle. 18. Address valid prior to or coincident with CE transition LOW. 19. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 20. Data I/O is high impedance if OE = VIH. 21. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 22. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 001-06511 Rev. *D
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Switching Waveforms
(continued) Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)[23, 24]
tWC
ADDRESS
CE tAW WE tSA tHA
tSD DATA I/O NOTE 25 tHZWE DATA VALID IN
tHD
tLZWE
Notes 23. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 24. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 25. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 001-06511 Rev. *D
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CY62256N
Typical DC and AC Characteristics
1.4 NORMALIZED ICC, ISB 1.2 NORMALIZED ICC 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN = 5.0V TA = 25C ICC NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 ISB2 A 0.8 0.6 0.4 0.2 0.0 VCC = 5.0V VIN = 5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC 3.0 2.5 2.0 1.5 1.0 0.5 0.0 25 125 -0.5 VCC = 5.0V VIN = 5.0V 25 105 AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE ISB STANDBY CURRENT vs. AMBIENT TEMPERATURE
55
55
SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA = 25C
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT (mA)
1.6 1.4 1.2 1.0 0.8 0.6
140 120 100 80 60 40 20
VCC = 5.0V
VCC = 5.0V TA = 25C
55
25
125
0 0.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT (mA)
120 100 80 60 40 20
VCC = 5.0V TA = 25C
0 0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Document Number: 001-06511 Rev. *D
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Typical DC and AC Characteristics
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED IPO DELTA tAA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 VCC = 4.5V TA = 25C
(continued)
NORMALIZED ICC vs. CYCLE TIME
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25
1.00
VCC = 5.0V TA = 25C VIN = 5.0V
0.75
600
800 1000
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Output Disabled Mode Deselect/Power down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Document Number: 001-06511 Rev. *D
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Ordering Information
Speed (ns) 55 Ordering Code CY62256NLL55SNXI CY62256NLL55ZXI CY62256NLL55ZXA CY62256NLL55SNXE CY62256NLL55ZXE 70 CY62256NLL70PXC CY62256NLL70SNXC CY62256NLL70ZRXI CY62256NLL70SNXA Package Diagram Package Type Operating Range Industrial Automotive-A Automotive-E Commercial Industrial Automotive-A 51-85092 28-pin (300-Mil) Narrow SOIC (Pb-free) 51-85071 28-pin TSOP I (Pb-free) 51-85071 28-pin TSOP I (Pb-free) 51-85092 28-pin (300-Mil) Narrow SOIC (Pb-free) 51-85071 28-pin TSOP I (Pb-free) 51-85017 28-pin (600-Mil) Molded DIP (Pb-free) 51-85092 28-pin (300-Mil) Narrow SOIC (Pb-free) 51-85074 28-pin Reverse TSOP I (Pb-free) 51-85092 28-pin (300-Mil) Narrow SOIC (Pb-free)
Do contact your local Cypress sales representative for availability of these parts
Ordering Code Definitions
CY 62 256 N LL - XX XXX X
Temperature Grade: X = C or I or A or E C = Commercial = 0 C to +70 C; I = Industrial = -40 C to +85 C; A = Automotive-A = -40 C to +85 C; E = Automotive-E = -40 C to +125 C Package Type: XXX = SNX or ZX or PX or ZRX SNX = 28-pin Narrow SOIC (Pb-free) ZX= 28-pin TSOP I (Pb-free) PX = 28-pin Molded DIP (Pb-free) ZRX = 28-pin Reverse TSOP I (Pb-free) Speed Grade: XX = 55 ns or 70 ns Low Power Nitride Seal Mask fix Density: 256 Kbit MoBL SRAM family Company ID: CY = Cypress
Document Number: 001-06511 Rev. *D
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Package Diagrams
Figure 10. 28-pin (600-Mil) Molded DIP, 51-85017
51-85017 *D
Figure 11. 28-pin (300-mil) SNC (Narrow Body), 51-85092
51-85092 *C
Document Number: 001-06511 Rev. *D
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CY62256N
Figure 12. 28-pin TSOP I (8 x 13.4 mm), 51-85071
51-85071 *H
Figure 13. 28-pin TSOP I (8 x 13.4 mm), 51-85074
51-85074-*F
Document Number: 001-06511 Rev. *D
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CY62256N
Document History Page
Document Title: CY62256N 256K (32K x 8) Static RAM Document Number: 001-06511 REV. ** *A *B *C ECN NO. Submission Date 426504 488954 2715270 2891344 See ECN See ECN 06/05/2009 03/12/2010 Orig. of Change NXR NXR New Data Sheet Added Automotive product Updated ordering Information table Added Table of Contents Removed "L" product information Updated Ordering Information table Updated Package Diagrams (Figure 10, Figure 11, and Figure 12) Updated Sales, Solutions, and Legal Information Updated Ordering Information. Added Ordering Code Definitions. Description of Change
VKN/AESA Updated POD of 28-Pin (600-Mil) Molded DIP package (Spec# 51-85017) VKN
*D
3119519
01/04/2011
AJU
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
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PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06511 Rev. *D
Revised January 4, 2011
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